1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and more particularly relates to a semiconductor integrated circuit device having a clock signal transmission line distributing a clock signal to a plurality of signal lines.
The present invention also relates to a wiring layout design method and a wiring layout design apparatus for designing clock signal transmission lines for distributing a clock signal to a plurality of signal lines.
2. Description of the Background Art
FIG. 13 is a block diagram showing the schematic configuration of a conventional semiconductor integrated circuit device.
Referring to FIG. 13, a sub-clock line 3 in a semiconductor integrated circuit device 10 is connected to a clock trunk 1 through a clock driver 2. A plurality of signal lines 4a to 4f are connected to sub-clock line 3. A plurality of latch circuits LT's are connected to each of signal lines 4a to 4f. 
A clock signal CLK is outputted from a clock circuit which is not shown in FIG. 13. Clock signal CLK is transmitted from clock trunk 1 to sub-clock line 3 through clock driver 2. Main drivers 5a to 5f are inserted into respective signal lines 4a to 4f. Main drivers 5a to 5f receive clock signal CLK from sub-clock line 3 and outputs clock signals CLK to the plural latch circuits LT's connected to signal lines 4a to 4f, respectively.
In FIG. 13, since the numbers of latch circuits connected to respective signal lines 4a to 4f are different, signal lines 4a to 4f have different connection capacities. The different connection capacities cause a clock skew.
On signal line 4a having the largest number of latch circuits connected thereto, a latch circuit LT1 is one connected to signal line 4a located at the farthest position from the node between signal line 4a and sub-clock line 3. On signal line 4f having the smallest number of latch circuits connected thereto, a latch circuit LT2 is one connected to signal line 4f located at the nearest position from the node between signal line 4f and sub-clock line 3. A large difference, i.e., a large clock skew is generated between time at which clock signal CLK outputted from clock driver 2 arrives at latch circuit LT1 and time at which clock signal CLK outputted from clock driver 2 arrives at latch circuit LT2. It is necessary to fall the clock skew within an allowable range. If a clock skew exceeding the allowable range occurs, circuits in the semiconductor integrated circuit device or the wiring layout thereof should be changed.